The invention relates generally to integrated circuits, and more particularly to low jitter external clocking.
Digital integrated circuit systems often include one or more processors, memory devices, and input/output devices that communicate with each other through a bus system. Each device includes an integrated circuit made up of an arrangement of logic gates, and each gate implements a logic function. The gates are interconnected and communicate with each other by changing state in unison at regular, timed intervals according to an internal clock signal. Information input to the integrated circuit, in the form of signals, is acted upon by the logic gates which produce new information as output signals.
Digital integrated circuits are typically timed by a clock generator that functions through a phase-locked loop. The phase-locked loop locks an internal clock signal in phase and frequency to an external input clock. The phase-locked loop has the capability to create additional clock signals with frequencies that are multiples of the frequency of the external input clock, while maintaining a phase relationship with the external input clock. In addition, the phase-locked loop rejects external input clock jitter. However, the phase-locked loop has a lock time requirement that delays a start-up of an integrated circuit from an idle/power-down state, and is a sophisticated analog circuit that does not scale easily with process changes.
In a very high frequency synchronous integrated circuit system, operating at gigahertz frequencies and higher, the phase-locked loop is used to multiply a frequency of an external input clock to generate a very high frequency internal clock signal in an integrated circuit in the system. In generating such high frequencies the phase-locked loop can contribute to jitter in the internal clock signal, and also suffers from problems of instability and noise. There remains a need for very high frequency synchronous integrated circuit systems that are timed in a manner to minimize jitter, instability, and noise in an internal clock signal.
According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.
Advantages of the invention will be apparent to one skilled in the art upon an examination of the detailed description.